In industry, there is a need that ICs should have a higher density and thus the size of the MOS transistor should be reduced. Scaling of MOS transistors, however, leads to two well-known parasitic effects, i.e., short channel effect and drain-induced barrier lowering effect due to the decreased gate length, and tends to deteriorate the electrical properties of the device, such as dropped gate threshold voltage, increased power consumption and decreased signal to noise ratio. Physically, these effects can be explained as follows: when the transistor is turned off (i.e., when the gate voltage is zero), the static electricity in the source/drain regions of very small devices or the voltage applied to the drain in the channel region may reduce the energy barrier of the electrons or holes in the channel, and may result in a higher turn-off current.
In order to control the short channel effect, more dopants such as phosphorus and boron have to be doped into the channel, which may possibly lead to decrease of carrier mobility in the device channel. In addition, it is also difficult to control the steepness of the doping profile of dopants in the channel, and may cause a serious short-channel effect. Moreover, the thickness of the gate oxide dielectric will also become a development bottleneck, and the speed at which the gate oxide thickness decreases is difficult to catch up with the decrease in the gate width. As a result, gate dielectric leakage becomes bigger and bigger. Continuous decrease of the critical dimension may result in increased resistance of the source and drain regions and increased power consumption of the device.
Short channel effect can be effectively controlled through the strained silicon technology. Strained silicon has been used as a substrate of the MOS transistors, wherein lattice constant difference between silicon germanium and monocrystalline silicon results in the strain of the structure of silicon germanium epitaxial layer so that strained silicon is formed. The lattice constant of silicon germanium layer is greater than that of silicon, which causes the mechanical stress in the channel region and thus the change of carrier mobility. In FET, the tensile stress can increase the electron mobility and reduce the hole mobility, which advantageously improves the performance of NMOS; and compressive stress can enhance the hole mobility and reduce the electron mobility, which advantageously improves the performance of PMOS.
However, the conventional silicon-germanium strained silicon technology is also confronted with a bottleneck. It is difficult for the channel to provide a stronger strain, and therefore the performance of semiconductor devices cannot be effectively enhanced.